Active power factor correction (PFC) techniques have evolved significantly over the past decade and a half in terms of knowledge base, component availability, design optimization and cost reduction. However, a large portion of the ATX power supplies required to meet the IEC 1000-3-2 requirements still use a passive PFC approach.
Despite the bulk and “clunkiness†of the passive inductor required, economic rationalizations are available for this choice. However, in the broader context of system optimization and end-customer preferences, these rationalizations may soon lose validity. End-user requirements for higher functionality and higher power levels are accompanied by the need for more compact solutions. In the active PFC realm, these demands are easier to satisfy than with the passive approaches.
A key issue to consider when choosing a harmonic reduction circuit is its impact on the rest of the system. We can quantify this effect by examining a 250-W ATX example. Fig. 2 shows the representative circuits for the active and passive approaches. The passive PFC solution requires a range switch and a voltage doubler to keep the bulk voltage relatively constant. The differences between the two approaches are quantified in Table 1.
One of the most significant benefits of the active PFC is realized in the design of the downstream SMPS converter. The minimum input voltage for the SMPS stage is increased (as shown in Table 1, 300 V versus 200 V for 250 W) for the same holdup time and for much smaller capacitor values.
With the narrower input voltage range, the SMPS design has a flexibility that can be exploited for lower system cost, better efficiency or both. For example, the rms current in the SMPS stage power MOSFET and the transformer is reduced by 33% (from 2.05 A to 1.36 A) with the inclusion of PFC stage, which leads to a 56% reduction in conduction losses in these elements if the same RDS(on) and wire gauge are used. Alternatively, lower-cost MOSFETs may be used to achieve the same conduction loss.
Another area where the active PFC solution helps is in meeting the holdup time (or line dropout) requirements — usually one line cycle at full load and low line. The active PFC boost naturally provides great holdup performance without requiring a large capacitance value since the energy is stored in boost output capacitor at a much higher voltage (~ 400 V).
Any non-PFC or passive-PFC solution stores the energy at the peak of the line voltage, which is about 140 V for low line (100 V). With the voltage doubler, this voltage becomes twice that value. The impact of this is reflected in the size of the holdup capacitor shown in Table 1. Remember that the values shown in Table 1 are for different minimum voltages. If the same minimum voltage were used, the difference in capacitance value would be much more pronounced.