I was going to upload a pic of my notes but they are really messy lol..
here's a link to a more accurate diagram;
http://static.commentcamarche.net/en.kioskea.net/faq/images/KjBt8WVH4Epro7ik.png
Im finding it hard to think of how to explain how it all works..
The CPU basically has components inside it, a control unit with priortises data or instructions, a execution unit (or units if you have multiple cores) which processes the data or instructions and registers (L1 - L2 caches) that store frequently used data so it doesn't have to grab it from the RAM.
you have two types of units in the execution unit, ALU and FPU.
ALU (arithmetic logic unit) handles most processes, best suited to whole numbers.
FPU (floating point unit) handles less process and is really just designed to deal with real numbers (very large, small or precise numbers).
I cant explain what it means by numbers, but I just know ALU does most the work lol.
with a single core, you have one execution unit so it orders, executes and then selectively stores strings of instructions in the registers.
With a multi core, each core can handle incoming strings of instructions or data simultaneously, e.g. when one core is executing instructions the other core can be storing instructions in the registers and another core can be executing data.
This is why its much faster.
L1 - L3 caches in the CPU
The level 1 cache is the fastest and smallest memory, level 2 cache is larger and slightly slower but still smaller and faster than the main memory, level 3 cache (main CPU memory) again usually is larger and slightly slower again then 2 and 1.
Data gets stored in each cache based on how frequently used it is, so if its being used alot! itll stay closest to the EU so it can process the data the fastest which would mean it stays in cache 1, then it would be 2, then 3 (if the CPU has L3) then back to the RAM, then HDD...
I may have not made this clear but im trying to explain the best I can lol. I may of missed a thing or two, just ask me and I could try and explain further.