Been saying for ages that high latency DDR is not a good combination with a low latency point to point bus regardless of clock frequencies
The one big question here is this bug in the memory controller. This review appears to have a chip with the bug, so I would have to guess that once that is corrected, Rev. F chips will indeed end up beating Rev E. But, at the same time, it does not appear by much.
I also think people are highly overestimating Conroe and it's derivitives
I would have to agree to a point, but it will definitely be a big leap for Intel nonetheless.
as I've also been saying all along they're going to get killed by the reliance on the external memory controller and the resulting I/O bandwidth limitations from it which is where AMD is going to pick up huge ground
The external memory controller is definitely an issue, but I would definitely not say 'killed.' As you mentioned here:
furthermore I fail to see what speculation there is with Conroe considering I've also been insisting for months that people read up on dothan...DOTHAN
Look at what Dothan has done with extremely limited bandwidth. A dothan in some benches beat a single core A64 clock for clock and this is with very low FSB compared to what Conroe will have. Many of the even highly OC'd Dothans were still only in the low to mid 200'sFSB. We will surely see 400+ even 500+ FSB with Conroe which will substantially increase bandwidth.
On another example, we do already have some Yonah benchmarks, and it has also done extremely well, also with a lower FSB than Conroe will have. So, while I agree that using the external memory conroller is not optimal, I really don't see it 'killing' the performance.
Lastly, there is definately still room for speculation with Conroe since it is far from just a desktop dothan, or even Yonah for that point. For example:
Improved decoder. Theinq.org hints to Macro-op fusion which meen that if you have a multiply followed by an add, Macro- op fusion can turn that into a multiply and Accumulate.
4-issue core instead of 3-issue in Yonah.
Better FPU which can handle two 64-bit fpu-operations per cycle (128-bit SSE2/SEE3/SSE4).
Yeah, but didn't some guy get a 23sec superpi 1m run with a 2.7GHz conroe?
That was Yonah, not Conroe.