No, Conroe is completely different than Brisbane. Brisbane is only a die shrink of K8, nothing more. Conroe is completely redesigned. The prefetching of the Conroe architecture is far more advanced than Brisbane. Also the quantity of IPCs executed is far greater with Conroe than Brisbane. Conroe is far superior than Brisbane.
well i guess ur right then best conroe is at 2.9ghz using 2+2mb cache ( Intel Core 2 Extreme X6800). While brisbane's best is 2.5 ghz and only 512+512kb cache (4800+). Though using old K8 archtiure made 5 years ago, its just normal for a new conroe made a couple months ago to beat down it.
isnt intel coming out with true quad core courter 3
once thats out i doubt amd will compete
cuz the poblem with ati and amd is there to slow to the market
amd will be ahead of intel core a month or to and then intel
will be out with somthing a lot better
More info on the new AMD CPUs
Core Enchancements:
128 Bit floating point:
* Applies only to Agena & Kuma
New SSE4A instructions:
* Advanced Bit manipulation
* MWAIT & MONITOR instructions
* Misaligned SSE Mode
Additional Features:
* Power management state invariant time stamp counter (TSC)
* increased number of TLB Page entries
* 1GB large paging support
* Physical address space increased to 48 bits
IMC Enhancements
DDR2 Dimms in products variations:
* Socket AM2+: Dual Channel unbuffered 1066 support
* Socket 1207+ Dual Channel unbuffered 1066 support
Memory Controller enhancements
* Write Burst & DRAM prefetching performance improovements
* DRAM writes can be buffered in the memory controller before being opportunistically bursted into DRAM controler to improve DRAM interface efficiency
* Read prefetcher detects stride paterns and issues prefetch requests based on confidence level
* Channel Interleaving
Roadmap:
Agena FX:
Q3 2007:
2.7-2.9GHz
2MB L2 total L2 cache for the CPU (quad core so 512KB each core)
2MB shared L3
Socket 1207+
4000MHz hypertransport Bus
TDP not determined yet
65nm SOI
Agena:
Q3 2007:
2.4-2.6GHz
2MB L2 total L2 cache for the CPU (quad core so 512KB each core)
2MB shared L3
Socket AM2+
4000MHz hypertransport Bus
TDP 125W
65nm SOI
Kuma:
Q3 2007:
2.0-2.9GHz
1MB L2 total L2 cache for the CPU (dual core so 512KB each core)
2MB shared L3
Socket AM2+
4000MHz hypertransport Bus
TDP 89w - 65w
65nm SOI
Same L2 cache but with added L3 cache and double hypertransport bus. Should make a difference. With Intel's coming 45nm Penryn proccesors, all i have read so far they are 3mbcache per core (Dual-core 6mb, Quad-Core 12mb) and clock speeds start at 3ghz reaching high over. Next generation's proccesors should be more fun to watch. Even with the release of Penryn (Late this year), AMD will have its 45nm proccesor ready "Shanghai" Opteron CPU a couple months after. Lets see how the tables turn.