Consider a 32 bit microprocessor with a 16 bit external data bus, driven by an 8 MHz i/p clk . Assume that this MuP has a bus cycle whose min duration equals for i/p clk cycle. What is the max. data transfer rate across the bus that this MuP can sustain in bytes. To increase the performance would it be better to make an external data bus, 32 bit or to double the external Clk freq supplied to the MuP? State any other assumptions.
Hint: determine the no of bytes that can be transferred.
Hint: determine the no of bytes that can be transferred.
