RAM latency..

[Chankama]

Hey guys. Any of you know how a ram latency can be a non-integer? I don't get it.

OCZ type a - 2.5 - 3 - 3 - 7
OCZ type b - 2 - 3 - 3 - 6

How can the first # of type a be "2.5" instead of 2 or 3. Also, what kind of performance gain can I expect between type a and b, with the stock settings.

 

[Nubius]

it's an increment in speed that's all.

Suppose that 1 = 30nanoseconds of time.

Then 2 would be 60nanoseconds

2.5 would be 75nanoseconds, 3 would be 90..

that's all it is.

Between type A and B you can expect absolutely no performance gain. Cas latency and cycle time ( the end number) effect stability not bandwidth really

 

[Chankama]

ah ic. I forgot that DDR does stuff in both the rising and falling edges of the clock cycles. I am presuming that 2.5 means two full clock cycles and 1/2 clock cycle (only the rising edge or the falling edge)?? Is this right?

And why doesn't type b have a increased performance man? I know paper figures and actual figures vary a lot.. But, 2 vs 2.5 seems to be a big increase - especially considering we do a lot of memory accesses. Thx.

 

[JSteez]

Latencies (2-2-2-5) determin the actual memory module's speed.

Frequencies (PC3200/DDR400/200 MHZ) determin the speed at which data is transfered between the memory module and memory controller.

 

[Nubius]

I am presuming that 2.5 means two full clock cycles and 1/2 clock cycle (only the rising edge or the falling edge)?? Is this right?

No dude...as I said it's an increment in time. You can have a Half of a second, it's not always rounded to a whole number.

2.5 is in terms of nanoseconds although I couldn't tell you exactly how much but I explained that in the first post.

Think of it was 2 and a half seconds if you want to to make it more clear.

But, 2 vs 2.5 seems to be a big increase - especially considering we do a lot of memory accesses. Thx.

If you don't have a complete understanding of how the timings work, how can you assume it's a big increase?

http://www.dfi-street.com/forum/showthread.php?s=&threadid=3393

Go there, scroll way down until you see big black text that says DRAM TIMINGS. The green text is your common timings and they will tell you what effect they have on RAM.

They effect stability, not bandwidth

 

[JSteez]

Nubius is completely right. Latencies have no effect on bandwidth.

 

[Chankama]

No dude...as I said it's an increment in time. You can have a Half of a second, it's not always rounded to a whole number.

2.5 is in terms of nanoseconds although I couldn't tell you exactly how much but I explained that in the first post.

Hey dude. After reading a few docs in the last 1/2 hour, I don't think that's quite accurate. This Wiki link (among others) indicates that the CAS # IS infact the # of clock cycles as I initially suspected. Which again raises the question of the 0.5 in "2.5". My hypothesis is that it is one of the rising/falling edges of the clock.

If you don't have a complete understanding of how the timings work, how can you assume it's a big increase?

http://www.dfi-street.com/forum/showthread.php?s=&threadid=3393

In anycase, that being said about the CAS #, the question I raised about 2.5 vs 2 was essentially about the performance gain by going from 2.5 clock cycles to 2 clock cycles to memory access. After all, without anything being a factor, (2.5 - 2)/2 is a huge performance reduction. But, as this article explains, it is NOT the only factor. It's a good read and lists other factors that make the performance gain not so much.

Nubius is completely right. Latencies have no effect on bandwidth.

I don't know how you can say this man. If you are talking about the full bandwidth of the memory (as in the information transferred per unit time), I would imagine that less delay within the memory unit would allow more information to be transferred in/out assuming the CPU is always querying the memory. After all, if the memory has a CAS latency of 2000 clock cycles (as opposed to 2 or 2.5 or 3), I would imagine the memory throughput of the memory unit would be pretty low.

 

[Nubius]

This Wiki link (among others) indicates that the CAS # IS infact the # of clock cycles as I initially suspected. Which again raises the question of the 0.5 in "2.5". My hypothesis is that it is one of the rising/falling edges of the clock.

Man...a clock cycle is a measurement of nanoseconds...I was trying to explain it in terms you could understand for a beginner. I never said that it WASNT a clock cycle, I merely was using different terms.

the .5 is not a seperate measurement dude. It's two and a half clock cycles. If a clock cycle is 30 nanoseconds, that means 2.5 would be 75 nanoseconds of time.

I've been doing this for a while man, I know what I'm talking about.

After all, without anything being a factor, (2.5 - 2)/2 is a huge performance reduction.

going from cas latency of 2 to even 3, is NOT a huge performance difference. It effects stability more-so than it does bandwidth, same goes for the cycle time...hence why you will see overclockers with timings like 2-2-2-11 because that 11 helps in stability not speed.

If you want to find out for yourself, run SiSoftware memory benchmark with cas latency 2.5, then raise it to 3..you'll see hardly any difference, and hell for all we know, that could just be the simple fact, that the tests even with the same settings wouldn't give you exact results each time.

 

[Chankama]

Man...a clock cycle is a measurement of nanoseconds...I was trying to explain it in terms you could understand for a beginner. I never said that it WASNT a clock cycle, I merely was using different terms.

lol. Yeah man. I think everyone on this board knows a clock cycle has a fixed time length . Thus, 2.5 clock cycles = cycle time * 2.5. I said what I said because when I made a statement about how 2.5 probably meant 2.5 clock cycles, you replied " No dude...as I said it's an increment in time. " - as if you didn't agree with the notion that it IS the # clock cycles at the top level.

Because of that it seemed like you were implying the "latency time" = "some fixed time interval T" * 2.5, where T != "cycle time". I was merely pointing out that the fixed time interval, T, you were referring to was infact the cycle time of the clock (and not some random fixed time interval), as per my 2nd post.

the .5 is not a seperate measurement dude. It's two and a half clock cycles. If a clock cycle is 30 nanoseconds, that means 2.5 would be 75 nanoseconds of time.

I've been doing this for a while man, I know what I'm talking about.

The original reason I posted this post was because the notion of an output being available in fractional clock cycles sounded strange. After all, the clocking process determines how the data moves from registers inside the components. And the clock cycle has to account for the settling time of the data given the intrinsic delays that are inherent to the design of the memory module. I just forgot that DDR does stuff in periods of 1/2 cycles - as in it's sensitive to both the rising AND falling edges. After all, a latency of 2.35 would not make any sense - even though its a physically realizable time in nanoseconds - for DDR anyways..

Damn. It's been a while since I've done any hardware designing. About 3 years ago I remember designing a CPU and a memory unit in VHDL, but it's amazing how fast technology evolves. Definitely need to read up more about the official DDR spec.

 

[Nubius]

No dude...as I said it's an increment in time. " - as if you didn't agree with the notion that it IS the # clock cycles at the top level.

Aright, I gotcha now, I see how we were misunderstanding each other there.

But you see why, it doesn't really effect bandwidth now though right? going from 2.5-3-3-7 to 2-3-3-6 won't give you any performance gain...if you get to the 'micro' level lol yeah I suppose it does, but in overall it's mainly for stability when OC'ing