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Old 01-13-2004, 02:20 PM   #1 (permalink)
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Default Logic Gates (Technical Question)

I couldnt find this question anywhere online so i thought id ask it here

The Bistable Latch is the elementary storage device for a single Bit. It was explained on the basis of two cross-coupled NAND-gates as steering logic. Provide a similar explanation of the latching action which is acheived with two cross-coupled NOR-gates operated with a further two NOR-gates as their steering logic.

Thanks it will help me out a lot
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Old 01-13-2004, 02:41 PM   #2 (permalink)
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You may want to refer this question to NASA.
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Old 01-13-2004, 02:44 PM   #3 (permalink)
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well it is a bit difficult because we are from the beagle team and don't want to admit defeat to NASA. Hopefully, the answer will allow us to figure out what went wrong and find the bloody thing!!
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Old 01-13-2004, 02:44 PM   #4 (permalink)
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is this like a test or something? been a while, but I will see what I can come up with...
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Old 01-13-2004, 02:51 PM   #5 (permalink)
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To the beagle team, keep your head up high. NASA didnt get where they are with out a history of problems. 1 step for man, one giant leap for aerospace contractors.
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Old 01-13-2004, 04:45 PM   #6 (permalink)
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Hmmmmm

WTF, mate? lol
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Old 01-14-2004, 12:31 PM   #7 (permalink)
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So, what your saying is you want to make an and out of two ors? - I thought that made the boat move!!!!!

See :

http://www.cs.kent.edu/~walker/class...ctures/L06.pdf

top of the first page... is that what you wanted?
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Old 01-14-2004, 12:43 PM   #8 (permalink)
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Question Bistable Latch and Logic Circuits

Hmmm...

The Flux Inhibitor must act as a salvo to the Lutrino Accelerator.. thus will the BLT be at its prime for delivery...

ANYHOW,,, check this out,,

hope it helps a bit,,,

cheers
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Old 01-14-2004, 12:55 PM   #9 (permalink)
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i know mike. i think they are speaking another language. just nod your head and pretend you follow it.
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Old 01-14-2004, 04:57 PM   #10 (permalink)
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a bi-stable latch is simply a latch which is stable in either 1 of 2 states until changed by its input.
In other words, the o/p of the latch will remain high (logic 1) until its input flips it back to a low (logic 0) and vice versa.
You can build latches out of different gates.
A NAND gate by definition is a gate which will provide you with a LOW level as long as all its inputs are high. By cross-coupling them, you can actually make them so that the o/p will change with the change of only one input.
A NOR gate will give you a LOW level as long as any of its inputs is high. Again, by cross-connecting them, you can achieve a variation of the o/p by only one of its inputs.

A much simpler latch model often used is a NPN transistor (or PNP with inverted bias voltage) with the emitter attached to the ground and the collector attached to a +5V bus through a resistor with a sample and hold cct in the biasing cct.

By applying a high level (logic 1) at the base of the transistor, the ground from the emitter is felt on the collector and a logic 0 is the result. By applying a low level (logic 0) on the base, the transistor is cut-off and the 5V is attached to the collector is now felt at the o/p giving you a logic 1 level.

Latches are often used to program logic ccts such as variable multipliers/dividers etc...
The CPU would load the latch to a certain value for a particular operation (say a variable divider from 1 to 8). In this example, a 3 bit latch o/p varying from 000 to 111 (binary 0 to 7) would be applied to the divider i/p and program it to the proper value. The divider would then allow the o/p of the divider to cycle every X number of pulses programmed by the latch which would effectively divide the clock by a value varying on the value loaded into the latch.
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