Intel Developer Forum 22nm Facts
Intel, in conjunction with the world's first demonstration of chips built on 22nm process technology, has posted a fact sheet today (.PDF) covering the highlights of the Intel's upcoming 22nm high-k metal gate process technology:
Intel, in conjunction with the world's first demonstration of chips built on 22nm process technology, has posted a fact sheet today (.PDF) covering the highlights of the Intel's upcoming 22nm high-k metal gate process technology:
SRAMs are used as test vehicles to demonstrate technology performance, process yield and chip reliability prior to ramping processors and other logic chips that will use the given manufacturing process.
Intel is now in full development mode on 22nm and on pace to continue the company's "tick- tock" model into the next generation.
The 22nm test circuits include both SRAM memory and logic circuits to be used on 22nm microprocessors.
SRAM cells of 0.108 and 0.092 square microns function in an array totaling 364 million bits. The 0.108 square micron cell is optimized for low voltage operation. The .092 square micron cell is optimized for high density and is the smallest SRAM cell in working circuits reported to date.
The test chip packs 2.9 billion transistors, at approximately double the density of the previous 32nm generation, in an area as small as a fingernail.
The 22nm dimensions are patterned with exposure tools using light with a wavelength of 193nm, a remarkable testament to the ingenuity of Intel's lithography engineers.
This 22nm technology continues to deliver the promise of Moore's Law: smaller transistors, improved performance/watt and lower cost per transistor.
Intel is now in full development mode on 22nm and on pace to continue the company's "tick- tock" model into the next generation.
The 22nm test circuits include both SRAM memory and logic circuits to be used on 22nm microprocessors.
SRAM cells of 0.108 and 0.092 square microns function in an array totaling 364 million bits. The 0.108 square micron cell is optimized for low voltage operation. The .092 square micron cell is optimized for high density and is the smallest SRAM cell in working circuits reported to date.
The test chip packs 2.9 billion transistors, at approximately double the density of the previous 32nm generation, in an area as small as a fingernail.
The 22nm dimensions are patterned with exposure tools using light with a wavelength of 193nm, a remarkable testament to the ingenuity of Intel's lithography engineers.
This 22nm technology continues to deliver the promise of Moore's Law: smaller transistors, improved performance/watt and lower cost per transistor.
