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Old 06-17-2004, 12:46 PM   #1 (permalink)
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Unhappy CAS Latency factor confusing me

Lets say you have a RAM that is 400mhz fast and that RAM has a CAS of 2. If data can be sent only every 2 clock cycles wouldn't the RAM seem like its only really 200 mhz fast?

400 divided by 2 =200

2- Because of CAS meaning data can be sent every two clock cycles.

400-Because thats the Speed of the RAM.

200-Because if data can only be sent from ram every two memory clocks then would'nt it seem like the ram speed is only 200mhz fast?

Thank you
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Old 06-17-2004, 03:58 PM   #2 (permalink)
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no. You are right when you say that 2 clock pulses are required for CAS(Column Address Strobe) but once a memory location has been reached, the data transfer rate will occur at your memory clock rate. Those timings only determine the access time of each memory location and not the transfer rate.
Naturally, the lower the timings the better the RAM and you will see a net improvement with high quality RAM over generic
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Old 06-17-2004, 06:18 PM   #3 (permalink)
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When memory location has been reached, how long untill it has to repeat the CAS Signal?
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Old 06-17-2004, 07:03 PM   #4 (permalink)
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OR, each part of a columm that passes a row contain 8 bits so that would mean for example, a Cell that has 4096 rows and 1024 columms. Once a row is activated a RAS to CAS delay takes place usually the delay is 2 to 3 memory clocks. Then after the RAS to CAS delay, the CAS delay occurs which is usually 2 to 3 memory clocks and all the 8 x 1024 worth of data in the row empties out at normal memory clock speeds, and after that the next row that contains the next needed data will be accessed and the CAS and other latencies begins on that row, Am I right?
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Old 06-17-2004, 08:46 PM   #5 (permalink)
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Information is stored by first separating the memory area into rows and columns. The capacity of the individual chips determines the number of rows and columns per module. When several arrays are combined, they create memory banks.

The chips are actually accessed by means of control signals such as row address strobe (RAS), column address strobe (CAS), write enable (WE), chip select (CS) and several additional commands (DQ). You also need to know something about which row is active in the memory matrix at any given moment.

In today's computers, a command rate is defined in BIOS - generally 1-2 cycles. This describes the amount of time it takes for the RAS to be executed after the memory chip has been selected.


The memory controller selects the active row. But before the row will actually become active so that the columns can be accessed, the controller has to wait for 2-3 cycles - tRCD (RAS-to-CAS delay). Then it sends the actual read command, which is also followed by a delay - the CAS latency. For DDR RAM, CAS latency is 2, 2.5 or 3 cycles. Once this time has lapsed, the data will be sent to the DQ pins. After the data has been retrieved, the controller has to deactivate the row again, which is done within tRP (RAS precharge time).

There is one more technical restriction - tRAS (active-to-precharge delay). This is the fewest number of cycles that a row has to be active before it can be deactivated again. 5-8 cycles are about average for tRAS.

Memory timings are generally cited in order of importance:

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Old 06-18-2004, 12:32 PM   #6 (permalink)
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Thanks for the information. But I have three make sure questions about it,

1- When the row is finally being read, that is when data moves out of the row at every memory clock, am I right?

2- About the TRAS latency when you said ---This is the fewest number of cycles that a row has to be active before it can be deactivated again--- Its the fewest number of cycles that a row has to be active before it can be deactivated while the other timings are going or is it a delay after all the timings took place?

3- Do these steps take place as well when data goes into ram?
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Old 06-19-2004, 05:48 AM   #7 (permalink)
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1- When the row is finally being read, that is when data moves out of the row at every memory clock, am I right?

with DDR 2 bits of info will move for every clock cycle therefore DDR 400 = 800

Those strobes (Column, Row etc....) are actually one single pulse that are 2 or 3 or whatever pulses in length. The CPU will address a column or row one at a time so they are not simultaneous. They occur during both read and write operations which is determined by one single line in your RAM stick. This signal tells the RAM if data is going to be stored or retrieved so those timings are necessary for both operations.
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