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Old 01-30-2007, 05:49 AM   #1 (permalink)
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Cool Ddr3,xxdr Ram,gddr Ram

The memory comes with a promise of a power consumption reduction of 40% compared to current commercial DDR2 modules, due to DDR3's 90nm fabrication technology, allowing for lower operating currents and voltages (1.5 V, compared to DDR2's 1.8 V or DDR's 2.5 V). "Dual-gate" transistors will be used to reduce leakage of current.

DDR3's prefetch buffer width is 8 bit, whereas DDR2's is 4 bit, and DDR's is 2 bit.

Theoretically, these modules could transfer data at the effective clockrate of 400-800 MHz (for a single clock bandwidth of 800-1600 MHz), compared to DDR2's current range of 200-533 MHz (400-1066 MHz) or DDR's range of 100-300 MHz (200-600 MHz). To date, such bandwidth requirements have been mainly on the graphics market, where vast transfer of information between framebuffers is required.

Prototypes were announced in early 2005, while the DDR3 specification is expected to be publicly available in mid-2007. Supposedly, Intel has preliminarily announced that they expect to be able to offer support for it in mid 2007 with a version of their upcoming Bearlake chipset. AMD's roadmap indicates their own adoption of DDR3 to come in 2008.

The GDDR3 memory, with a similar name but an entirely dissimilar technology, has been in use for several years in high-end graphic cards such as ones from NVIDIA or ATI Technologies, and as main system memory on the Xbox 360. It is sometimes incorrectly referred to as "DDR3".

Initially XDR DRAM will be offered at 3.2GHz with a roadmap to 6.4GHz and beyond, enabling memory system bandwidths up to 100GB/s. XDR DRAM will be available in multiple speed bins, device densities, and device widths. With densities ranging from 256Mb to 8Gb, and device widths ranging from x1 to x32, XDR DRAM satisfies the needs of both high-bandwidth and high-capacity systems. XDR memory's novel matrix topology allows point-to-point differential data interconnects to scale to multi-GHz speeds, while the bussed address and command signals allow a scalable range of memory system capacity supporting from one to 36 DRAM devices.

The company's family of double data rate (DDR) memory controller interface cells provides support for DDR1 and DDR2 operating at data rates up to 800 MHz and graphics DDR, including GDDR1, GDDR2, and GDDR3 up to 1,600 MHz. The controller interface cells are full-featured, drop-in physical layer (PHY) cells that employ established technology. They also emerge as the only such components to offer an optional performance mode to support XDR DRAM, said to yield a two-to-eight times increase in system memory bandwidth. With this option, users can develop a single chip that spans multiple price/performance points depending on which memory type is in use. In addition to interfaces, the company is offering related engineering services.
I hope to help u with the differnt ram types!!!
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