CntdwnToExtn
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Intel Core i7 = TLB
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veedubfreak
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I remember asking this when the phenoms came out, and i'll ask it again. Who does TLB actually affect?
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CntdwnToExtn
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This is what was happening to AMD. I can only assume this is what's happening to Intel?
DailyTech - Understanding AMD's "TLB" Processor Bug
So going by that, I would think Servers would see this A LOT more than Desktops since the up time would greatly increase the chance.
Someone like MasterCard who can do millions of transactions per day - not a good thing.
DailyTech - Understanding AMD's "TLB" Processor Bug
So going by that, I would think Servers would see this A LOT more than Desktops since the up time would greatly increase the chance.
Someone like MasterCard who can do millions of transactions per day - not a good thing.
veedubfreak
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Ya thats what i was under the assumption with the amd chips. This wont really affect desktop users for the most part.
Wildside
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fixed
.the media, and Intel, gave AMD a bad name because of this, u could say just labeling them about doing a poor job in keeping AMD CPUs bug free.
Puddle Jumper
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Until a more reputable source confirms it I wouldn't take this too seriously. Fudzilla has had articles that were completely wrong before.
NosBoost300
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amd had a tlb errata problem.. big difference.. intel core 2 duo's also tlb...
and to veedub.. here is intels old tlb
Chip bugs
The Core 2 memory management unit (MMU) in X6800, E6000 and E4000 processors does not operate to previous specifications implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the Translation Lookaside Buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data."[55]
Among the issues noted:
* non-execute bit is shared across the cores.
* Floating point instruction non-coherencies.
* Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious.[56] 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent steppings.
Among those who have noted the errata to be particularly serious are OpenBSD's Theo de Raadt[57] and DragonFly BSD's Matthew Dillon.[58] Taking a contrasting view was Linus Torvalds, calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better."[59]
Microsoft has issued update KB936357 to address the errata by microcode update, with no performance penalty. BIOS updates are also available to fix the issue.
only you know... intel didnt have a HUGE problem like amd did.. and i'm sure they don't now...
core i7 errata problems
Errata (Sheet 1 of 3)
Number
Steppings
Status ERRATA
C-0
AAJ1 X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error
AAJ2 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints
AAJ3 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAJ4 X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode
AAJ5 X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAJ6 X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations
AAJ7 X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
AAJ8 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AAJ9 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AAJ10 X No Fix MOV To/From Debug Registers Causes Debug Exception
AAJ11 X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update
AAJ12 X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AAJ13 X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
AAJ14 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AAJ15 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception
AAJ16 X No Fix General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted
AAJ17 X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit
AAJ18 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode
AAJ19 X No Fix Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter may be Incorrect
AAJ20 X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
AAJ21 X No Fix Use of Memory Aliasing With Inconsistent Memory Type May Cause Unpredictable System Behavior
AAJ22 X No Fix Delivery Status of the LINT0 Register of the Local Vector Table May be Lost
AAJ23 X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
AAJ24 X No Fix #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code
AAJ25 X No Fix Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction
AAJ26 X No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception
AAJ27 X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1
AAJ28 X No Fix Intel® QuickPath Memory Controller tTHROT_OPREF Timings May be Violated During Self Refresh Entry
AAJ29 X No Fix Processor May Over Count Correctable Cache MESI State Errors
AAJ30 X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work
AAJ31 X No FIx Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio
AAJ32 X Plan Fix The PECI Throttling Counter May Not be Accurate
AAJ33 X No Fix PECI Does Not Support PCI Configuration Reads/Writes to Misaligned Addresses
AAJ34 X No Fix OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal Error
AAJ35 X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt
AAJ36 X Plan Fix A Processor Core May Not Wake Up from S1 State
AAJ37 X Plan Fix Reading Reserved APIC Registers May Not Signal an APIC Error
AAJ38 X Plan Fix A Logical Processor Receiving a SIPI After a VM Entry Into WFS State May Become Unresponsive
AAJ39 X No Fix Memory Controller May Deliver Incorrect Data When Memory Ranks Are In Power-Down
AAJ40 X No Fix Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
AAJ41 X Plan Fix A Floating-Point Store Instruction May Cause an Unexpected x87 FPU Floating-Point Error (#MF)
AAJ42 X Plan Fix Incorrect TLB Translation May Occur After Exit From C6
AAJ43 X Plan Fix USB 1.1 ISOCH Audio Glitches with Intel® QuickPath Interconnect Locks and Deep C-States
AAJ44 X Plan Fix Stack Pointer May Become Incorrect In Loops With Unbalanced Push and Pop Operations
AAJ45 X No Fix A P-state Change While Another Core is in C6 May Prevent Further C-state and Pstate Transitions
AAJ46 X Plan Fix Certain Store Parity Errors May Not Log Correct Address in IA32_MCi_ADDR
AAJ47 X No Fix xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode
AAJ48 X No Fix Certain Undefined Opcodes Crossing a Segment Limit May Result in #UD Instead of #GP Exception
AAJ49 X No Fix Indication of A20M Support is Inverted
AAJ50 X No Fix Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures
AAJ51 X Plan Fix After VM Entry, Instructions May Incorrectly Operate as if CS.D=0
AAJ52 X Plan Fix Spurious Machine Check Error May Occur When Logical Processor is Woken Up
AAJ53 X No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
AAJ54 X No Fix Core C6 May Clear Previously Logged TLB Errors
AAJ55 X Plan Fix Processor May Hang When Two Logical Processors Are in Specific Low Power States
AAJ56 X Plan Fix MOVNTDQA From WC Memory May Pass Earlier Locked Instructions
AAJ57 X No Fix Performance Monitor Event MISALIGN_MEM_REF May Over Count
AAJ58 X No Fix Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations
AAJ59 X Plan Fix Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB Translation
AAJ60 X Plan Fix The "Virtualize APIC Accesses" VM-Execution Control May be Ignored
AAJ61 X Plan Fix C6 Transitions May Cause Spurious Updates to the xAPIC Error Status Register
AAJ62 X Plan Fix Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write Major Mode Enabled
AAJ63 X Plan Fix Running with Write Major Mode Disabled May Lead to a System Hang
AAJ64 X No Fix Memory Controller Address Parity Error Injection Does Not Work Correctly
AAJ65 X No Fix Memory Controller Opportunistic Refreshes Might be Missed
AAJ66 X Plan Fix Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP Onto The Stack
AAJ67 X Plan Fix The Combination of a Bus Lock and a Data Access That is Split Across Page Boundaries May Lead to Processor Livelock
AAJ68 X Plan Fix CPUID Instruction Returns Incorrect Brand String
AAJ69 X Plan Fix An Unexpected Page Fault or EPT Violation May Occur Following the Unmapping and Re-mapping of a Page
AAJ70 X No Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6
AAJ71 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
AAJ72 X No Fix EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine
AAJ73 X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
AAJ74 X No Fix PEBS Records For Load Latency Monitoring May Contain an Incorrect Linear Address
AAJ75 X No Fix PEBS Field “Data Linear Address†is Not Sign Extended to 64 Bits
AAJ76 X Plan Fix Core C6 May Not Operate Correctly in the Presence of Bus Locks
AAJ77 X No Fix Intel® Turbo Boost Technology May be Limited Immediately After Package C-state Exit with QPI L1 Mode Disabled
and to veedub.. here is intels old tlb
Chip bugs
The Core 2 memory management unit (MMU) in X6800, E6000 and E4000 processors does not operate to previous specifications implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the Translation Lookaside Buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data."[55]
Among the issues noted:
* non-execute bit is shared across the cores.
* Floating point instruction non-coherencies.
* Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious.[56] 39, 43, 79, which can cause unpredictable behavior or system hang, have been fixed in recent steppings.
Among those who have noted the errata to be particularly serious are OpenBSD's Theo de Raadt[57] and DragonFly BSD's Matthew Dillon.[58] Taking a contrasting view was Linus Torvalds, calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better."[59]
Microsoft has issued update KB936357 to address the errata by microcode update, with no performance penalty. BIOS updates are also available to fix the issue.
only you know... intel didnt have a HUGE problem like amd did.. and i'm sure they don't now...
core i7 errata problems
Errata (Sheet 1 of 3)
Number
Steppings
Status ERRATA
C-0
AAJ1 X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error
AAJ2 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints
AAJ3 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAJ4 X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode
AAJ5 X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAJ6 X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations
AAJ7 X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
AAJ8 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AAJ9 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AAJ10 X No Fix MOV To/From Debug Registers Causes Debug Exception
AAJ11 X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update
AAJ12 X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AAJ13 X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
AAJ14 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AAJ15 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception
AAJ16 X No Fix General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted
AAJ17 X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit
AAJ18 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode
AAJ19 X No Fix Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter may be Incorrect
AAJ20 X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
AAJ21 X No Fix Use of Memory Aliasing With Inconsistent Memory Type May Cause Unpredictable System Behavior
AAJ22 X No Fix Delivery Status of the LINT0 Register of the Local Vector Table May be Lost
AAJ23 X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
AAJ24 X No Fix #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code
AAJ25 X No Fix Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction
AAJ26 X No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception
AAJ27 X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1
AAJ28 X No Fix Intel® QuickPath Memory Controller tTHROT_OPREF Timings May be Violated During Self Refresh Entry
AAJ29 X No Fix Processor May Over Count Correctable Cache MESI State Errors
AAJ30 X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work
AAJ31 X No FIx Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio
AAJ32 X Plan Fix The PECI Throttling Counter May Not be Accurate
AAJ33 X No Fix PECI Does Not Support PCI Configuration Reads/Writes to Misaligned Addresses
AAJ34 X No Fix OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal Error
AAJ35 X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt
AAJ36 X Plan Fix A Processor Core May Not Wake Up from S1 State
AAJ37 X Plan Fix Reading Reserved APIC Registers May Not Signal an APIC Error
AAJ38 X Plan Fix A Logical Processor Receiving a SIPI After a VM Entry Into WFS State May Become Unresponsive
AAJ39 X No Fix Memory Controller May Deliver Incorrect Data When Memory Ranks Are In Power-Down
AAJ40 X No Fix Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
AAJ41 X Plan Fix A Floating-Point Store Instruction May Cause an Unexpected x87 FPU Floating-Point Error (#MF)
AAJ42 X Plan Fix Incorrect TLB Translation May Occur After Exit From C6
AAJ43 X Plan Fix USB 1.1 ISOCH Audio Glitches with Intel® QuickPath Interconnect Locks and Deep C-States
AAJ44 X Plan Fix Stack Pointer May Become Incorrect In Loops With Unbalanced Push and Pop Operations
AAJ45 X No Fix A P-state Change While Another Core is in C6 May Prevent Further C-state and Pstate Transitions
AAJ46 X Plan Fix Certain Store Parity Errors May Not Log Correct Address in IA32_MCi_ADDR
AAJ47 X No Fix xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode
AAJ48 X No Fix Certain Undefined Opcodes Crossing a Segment Limit May Result in #UD Instead of #GP Exception
AAJ49 X No Fix Indication of A20M Support is Inverted
AAJ50 X No Fix Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures
AAJ51 X Plan Fix After VM Entry, Instructions May Incorrectly Operate as if CS.D=0
AAJ52 X Plan Fix Spurious Machine Check Error May Occur When Logical Processor is Woken Up
AAJ53 X No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
AAJ54 X No Fix Core C6 May Clear Previously Logged TLB Errors
AAJ55 X Plan Fix Processor May Hang When Two Logical Processors Are in Specific Low Power States
AAJ56 X Plan Fix MOVNTDQA From WC Memory May Pass Earlier Locked Instructions
AAJ57 X No Fix Performance Monitor Event MISALIGN_MEM_REF May Over Count
AAJ58 X No Fix Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations
AAJ59 X Plan Fix Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB Translation
AAJ60 X Plan Fix The "Virtualize APIC Accesses" VM-Execution Control May be Ignored
AAJ61 X Plan Fix C6 Transitions May Cause Spurious Updates to the xAPIC Error Status Register
AAJ62 X Plan Fix Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write Major Mode Enabled
AAJ63 X Plan Fix Running with Write Major Mode Disabled May Lead to a System Hang
AAJ64 X No Fix Memory Controller Address Parity Error Injection Does Not Work Correctly
AAJ65 X No Fix Memory Controller Opportunistic Refreshes Might be Missed
AAJ66 X Plan Fix Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP Onto The Stack
AAJ67 X Plan Fix The Combination of a Bus Lock and a Data Access That is Split Across Page Boundaries May Lead to Processor Livelock
AAJ68 X Plan Fix CPUID Instruction Returns Incorrect Brand String
AAJ69 X Plan Fix An Unexpected Page Fault or EPT Violation May Occur Following the Unmapping and Re-mapping of a Page
AAJ70 X No Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6
AAJ71 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
AAJ72 X No Fix EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine
AAJ73 X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
AAJ74 X No Fix PEBS Records For Load Latency Monitoring May Contain an Incorrect Linear Address
AAJ75 X No Fix PEBS Field “Data Linear Address†is Not Sign Extended to 64 Bits
AAJ76 X Plan Fix Core C6 May Not Operate Correctly in the Presence of Bus Locks
AAJ77 X No Fix Intel® Turbo Boost Technology May be Limited Immediately After Package C-state Exit with QPI L1 Mode Disabled
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CntdwnToExtn
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Fudzilla has a direct link to Intel's documentation
That is why I posted it.
Can't get any more official than that XD
http://download.intel.com/design/processor/specupdt/320836.pdf
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