To be accurate, the so-called Grape DR chip is a maths co-processor. It's designed to sit on a PCI-X add-in card and provide back-up for the host system's CPU. And each core is designed to handle a single, specific maths instruction, such as a floating-point addition or multiplication. The chip also contains a shared memory cache.
The 512 cores are split into 16 groups of 32, each group capable of processing a single type of FP instruction. The chip itself measures 17 x 17mm and contains 300m transistors. It consumes up to 60W of power.
The University of Tokyo began work on Grape DR in 2004. By 2008, it hopes to have a design capable of delivering 2Pflops - two quadrillion floating-point operations a second.
http://www.channelregister.co.uk/2006/11/06/japan_512-core_co-pro/
The 512 cores are split into 16 groups of 32, each group capable of processing a single type of FP instruction. The chip itself measures 17 x 17mm and contains 300m transistors. It consumes up to 60W of power.
The University of Tokyo began work on Grape DR in 2004. By 2008, it hopes to have a design capable of delivering 2Pflops - two quadrillion floating-point operations a second.
http://www.channelregister.co.uk/2006/11/06/japan_512-core_co-pro/
