"Netburst" is a nickname that refers to the core design of Pentium 4 procesors such as the Presler 965 you've listed above, it has nothing to do with C2D processors.
I'm pretty sure that massacreinfallx was talking about the unified cache found on Conroe chips. This just means that the extremely fast ondie memory that the core uses is accessible to both cores. In other words, say you're running a single threaded app and one core is idle, the other core is free to use the entire 4MB cache. Previously, multicore processors have cores with dedicated cache, or they each had 2MB, and they could not "share" each others cache
Now, a processor executes an operation via sending a thread down a "pipeline" that has various stages that analyze and decode the thread so the processor can execute it. The number of stages defines the length of the pipeline. Presler was based on the Prescott revision and probably had 31 pipeline stages, whereas Conroe/C2D has 14 pipeline stages. The longer a pipeline is, the easier it is for the core to scale in terms of clock frequency which is why the Presler has a faster operating frequency.
However, an clock cycle is defined as the time it takes the core to execute an operation. You should be able to understand that a core with a shorter pipeline is able to execute an operation much faster than a core with a longer pipeline because the thread has to go through less stages. Therefore, the time it takes a 14 stage core to execute an operation is less than a 31 stage core, therefore the clock cycle of the 14 stage core is more efficent, therefore it requires less cycles to perform a similar operation when compared to a 31 pipeline core, therefore it can operate at a slower frequency and still perform at the same, or even greater speeds.
The megahertz wars as they have been labelled are irrelevant now, you have to factor in the IPC (instruction per cycle) rate of a core in order to determine its power.
