no, I did mean silicon-germanium transistors. IBM and AMD are developing them together.
http://news.zdnet.com/2100-9584_22-5982887.html
although yes, AMD may use Nickel Silicide aswell (which I admit I didn't know before)
and please don't try and attack me. If I'm wrong, you can correct me without comments like these:
Please get your terms right and not make such an amateur mistake again.
Infomatic said:
Moving to a smaller production size does not improve efficiency...it simply allows for a bit higher clockability and less power consumption.
less power consumption. that's what I mean by efficiency.
plus there's the lower production costs.
DDR2 won't show any performance increases.
can you say that for certain?
yes, current AM2 CPU's are not that great. but they are AMD's first chips to use DDR2. and their memory controller really needs improving.
"Improving the architecture's efficiency." That is a result, not an action. You need to explain how they are accomplishing this, or else its nothing.
I don't know exactly how, since I don't work for AMD. but it will involve changing the architecture to process more instructions/clock cycle, like they did from K7 to K8. K8 chips don't need as high frequencies to get the same performance as K7 chips.
As for the Silicon-Germanium transistors...where did you get that? I know those are the same ones used in that IBM chip, but where did you get that they're going to be using those in K8L? [/B]
I can't say for certain they
will be used on K8L, but I'd say it's pretty likely IMO.
http://www.hi-techreviews.com/modules.php?name=News&file=article&sid=7156
So what can we expect from the first 65 nm parts off the line? Probably something that few folks actually expect. Let me delve into one of the more overlooked properties of transistor design (well, at least to laymen like me). Basically the more stages in a pipeline means that the propagation delay in a signal is cut down and overall clockspeed can be increased, but more stages means that more transistors are being used. AMD is working with several partners to make sure that its 65 nm process is world class. This process encompasses embedded SiGe with dual stress liner and stress memorization technology on silicon on insulator- or e-SiGe with DSL and SMT on SOI for those so inclined. AMD and IBM have stated publicly that this technology allows for a 40% faster switching transistor than from a standard 65 nm design without all the three letter acronyms (TLAÂ’s). In a complex design like a CPU this could mean a theoretical 50% overall clockspeed increase going from AMDÂ’s 90 nm process to AMD/IBMÂ’s 65 nm process all the while staying within the same power envelope.
