REVERSE Hyperthreading for AM2!

[Sui]

OOOO you said the c word!

ehhh yeah I like watching the zombies walk too.

 

[reggie_da_man]

ehhh yeah I like watching the zombies walk too.

lol.

 

[Tyler1989]

Nothing on AMD's roadmap suggests that consider it a false rumor.

 

[Nitestick]

ok to see what is happening here almost makes me cry. flanker let sleeping dogs lie, no need for a vendetta. if you can't stand the attitude of people here and believe the mods hate you i see no incentive for you to come here other than to flame and argue. if that is the case you have no purpose here. leave us alone

it actually depresses me that you waste all your intelligence on bigoted posts. the reality is this: THE WORLD IS NOT AGAINST YOU!!!!!!!

THE WORLD IS NOT AGAINST YOU!!!!!!!
THE WORLD IS NOT AGAINST YOU!!!!!!!
THE WORLD IS NOT AGAINST YOU!!!!!!!

you don't need to be so defensive of your point and aggressive towards others. your message is being heard loud and clear (by some), most of all by me who you are so aggressive towards. those who aren't understanding your points aren't worth arguing with. you interpret everything i say through your defensive mindset as disagreeing. i haven't disagreed at all.

"If you argue with an idiot, he will drag you down to his level and beat you down with his experiance..." -Flanker

according to another user you said this profound sentence, keep that philosophy in mind regardless of whether or not you said it

this RHT rumour in my opinion is false. the only way it could work would be to split instructions in half but that doesn't seem achievable.

 

[reggie_da_man]

Couldn't AMD write some drivers for either Windows or the bios?

 

[Apokalipse]

this RHT rumour in my opinion is false. the only way it could work would be to split instructions in half but that doesn't seem achievable.

or to send every second instruction to the second core

I have been digging around, and I think this is what AMD is doing for K8L:

• moving to 65nm (will improve efficiency and clockability)
  
• improving and fixing bugs in the DDR2 memory controller (they need to anyway)
  
• improving the architecture's efficiency (more instructions/clock cycle)
  
• using silicon-germanium transistors, to decrease their switching time (by about 30% I think)
  
• adding another complex instruction decoder (from 3 to 4)
  
• Reverse Hyperthreading (maybe, maybe not)

so if AMD does all this (ad maybe more) then K8L should be quite good

 

[reggie_da_man]

Yea they use Silicon-germanium in the beast of an IBM CPU @ 500GHz.

 

[Infomatic]

Moving to a smaller production size does not improve efficiency...it simply allows for a bit higher clockability and less power consumption.

DDR2 won't show any performance increases.

"Improving the architecture's efficiency." That is a result, not an action. You need to explain how they are accomplishing this, or else its nothing.

The additional complex instruction decoder may indeed help, but not enough.

Reverse HyperThreading - Um...maybe not, lol.

I think that the maximum performance increase possible from Conroe is going to be 20%. No more, it just won't happen. Not from an architectural revision.

As for the Silicon-Germanium transistors...where did you get that? I know those are the same ones used in that IBM chip, but where did you get that they're going to be using those in K8L?

 

[Nitestick]

hmmmm i have also read about AMD planning to use SiGe chips but i don't know if thats true. Intel currently use a tiny amount of Germanium in their "strained silicon". should be interesting. i'm curious as to how IBM managed to get this chip working at such a high frequency at approx. 3 degrees above absolute zero. i was under the impression that at that temperature a) volume of all substances became miniscule-unmeasurable and b) electronic activity slows.

or to send every second instruction to the second core

i can't believe i never saw it that way . ultimately if it were possible to split an instruction (which i don't think you can) it would be better as that would basically yield a 100% increase in performance as both cores should be used to full power. alternating the instructions would work though i think it would give between a 30-60% in efficiency (i really kind of pulled that number from my butt, but it sounds about right to me) as inevitably one core would have to wait for the other core to finish its instruction before it could continue.

 

[Orayn]

RHT brings up a very interesting possibility. If it can, in fact, be used to create a virtual dual core on 4X4, AMD could really be on to something. Conroe killer? If the rumours are true, and the prices on AM2 drop enough, maybe.