robdarftw
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What are good memory timings for high performance games and applications, and what is a good cas latency for that also?
it all depends on what speed your memory is operating at... JEDEC standards specify 5-5-5-15 to be the standard timings at 667MHz... many (in fact almost all) DIMMs will support far tighter timings than this by utilising higher voltages (JEDEC specifies 1.8V)... as mentioned before, PC2-6400 DIMMs will usually operate at 4-4-4-12 and PC2-8500 will operate at 5-5-5-15. the tighter you can get your timings, the higher your memory bandwidth will be, thus dramatically increasing your performance.
i'll explain the basic memory timings, and their influence on your performance
CAS Latency (aka tCL) - this stands for Column Address Strobe and determines the delay between sending a read command and acting upon that command. Lowering this timing will increase your read speeds in an inversely proportional relationship with the change in timing (ie dR ~ 1/dT)
tRCD (RAS to CAS Delay) - this represents the delay between the activate and read/write commands on any given bank... tightening this timing will increase both the read and write speeds. a direct relationship is rather complex, and inaccurate at best owing to the fact that the tCL factor must be accounted for
tRP(Row Precharge) - defines the minimum delay between the next bank's activate and the last read/write commands... tightening this allows your CPU to address the banks faster, thus markedly increasing your memory bandwidth
tRAS (Row Address Strobe) - defines the minimum time between the activation and deactivation of a row. it effectively denotes the minimum time in which actions may be taken on any given bank... lowering this allows your memory to begin reading from/writing to the next bank more rapidly... if this is set too low the row may be deactivated before the read/write is complete, thus causing data corruption... as a rule, your tRAS should be set as tCL + tRCD + tRP (possibly +1 if this is too tight for your memory)
NOTE: all timings are in clock cycles, and as such should be increased at higher speeds (as more cycles occur per second) because of the physical limitations of solid state memory
mine are 5-5-5-15-26, 944. I'm gonna change it to 5-5-5-12-24 but i want my computer to be stable.
dude... read my previous post in this thread... never lower your tRAS more than 1 cycle below the sum of your other primary timings... the 3 cycle difference will give you fairly common data corruption and frequent system crashes... especially when loading large apps like games... i can see 4-5-5-15 or 5-5-4-15 or even 5-5-5-14, but that tRAS is way too low for the rest of those timings...