960 vs 1150 ddr2

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loose/high is higher score for intel
and tight/low is higher score for AMD?

yeah pretty much. i know that if i run my cpu full tilt and my ram overclocked to max, my (super pi/ 3dm06) scores are a little better than if i run my cpu full tilt and keep my ram tight (like 3-3-3-9 tight). but not nearly enough to warrant running the ram that hot.
memory benchmarks will put the lower latency set up a little on top. plus yes amd's (from my experience) tend to like low latency. i forget the formula, but running ram at 3-3-3-9 1T at or under 800mhz is not much different than running it at like 1100mhz with 5-5-5-15 2T. but its a lot cooler.
what jumping bean says above is one thing that is different with intel/amd...
amd has no fsb, so there is no bottleneck between the cpu and memory (unless it runs faster than 2000mhz).
 
htt, yes...but it isnt really like FSB...it takes the place of the front side bus.
its more like...."here's your info, take it" versus the FSB which is like "you want that info, let me go get it and i'll bring it back".
lol a little more complicated than that but i am going to the bar, so google it...its a significant difference. and probably will really come into play with K10 cpus.
 
It has to do with the memory controller being on the CPU (AMD) as apposed to on the motherboard (Intel). While having the controller on the CPU allows for faster communication, it take up needed space. Which is one of the reasons Intel CPU's typically have larger cache sizes.
 
the main reason for intels larger cache size is because they need the extra storage due to the delay of cpu->memory communication. ie, cpus with an on die memory controller have faster communication with the physical memory, hence the lower cache size of amd cpus...amds dont NEED 4mb of cache.
the reason c2d works as well as it does (memory wise) is becasue it currently has a superior prefetching system, not because it has a larger cache.
 
the main reason for intels larger cache size is because they need the extra storage due to the delay of cpu->memory communication. ie, cpus with an on die memory controller have faster communication with the physical memory, hence the lower cache size of amd cpus...amds dont NEED 4mb of cache.
the reason c2d works as well as it does (memory wise) is becasue it currently has a superior prefetching system, not because it has a larger cache.

I didn't say that it worked well because of the cashe size... but ok.
 
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