A computer consist of a CPU & an I/O device D, connected to MM,M viashared bus with a data bus width of one word. THe CPU can execute a max of 10 raised to 6 instrn/sec. An average instruction requires 5 machine cycles, 3 of which use the memory bus. A memory read/write oprn uses 1 machine cycle. Suppose that CPU is continously executing background pgms that require 45% of its instrn execution rate. But not any I/O instrn. Assume that the processor cycle =1 bus cycle. Now suppose very large bulk of data are to be transferred between M & D. If a pgmed I/O is used & each of one word I/O transfer requires the CPU to execute 2 instrns.
i) Estimate max I/O transfer of data in words/sec, possible thro D.
ii) Estimate the same rate if DMA transfer is used.
i) Estimate max I/O transfer of data in words/sec, possible thro D.
ii) Estimate the same rate if DMA transfer is used.
